The present invention generally relates to non-volatile semiconductor memory devices such as electrically-erasable programmable read-only memories (EEPROMs) and data processors that use such non-volatile semiconductor memory devices. More particularly, the present invention relates to a data processing system that uses a non-volatile semiconductor memory device for storing both programs and data, wherein runaway of the system is effectively eliminated without causing a decrease in the system throughput, by way of adding a simple circuit.
Today, EEPROMs include various circuits such as a write control circuit and a high voltage generator and can be used similarly to a static random access memory (SRAM). In spite of these various improvements, however, the EEPROMs still have problems such as a long write interval, and associated with this, there has been a problem of slow accessing due to the fact that the reading of data cannot be started until the writing of data is completed.
FIG. 1 shows a typical construction of a conventional EEPROM.
Referring to FIG. 1 showing a part of a data processing system that includes a CPU 40 and EEPROM 60', it will be noted that the CPU 40 and the EEPROM 60' are connected with each other by a system bus IBUS that in turn includes a control bus CBUS, a data bus DBUS and an address bus ABUS.
The CPU 40 includes various elements wherein FIG. 1 shows only those elements that will be described later. These elements include a program counter 21, an instruction decoder 22 and an execution unit 23.
The EEPROM 60', in turn, includes a memory cell array 1 in which memory cells are arranged in rows and columns, an address latch 2 supplied with address data from an external address circuit for latching the same, an input/output buffer 3 for receiving and outputting data, a data latch 4 supplied with input data from an external circuit via the input/output buffer 3 for latching the same, a sense amplifier 5 for amplifying data read out from the memory cell array 1, a timer 6 for counting time, a write control circuit 7 controlled by control signals such as an output enable signal OE# and a write enable signal WE# as well as by the timer 6 for controlling the writing operation of the EEPROM 60', and a high voltage generator 8 that boosts an externally supplied power voltage (5 volts) to produce a boosted voltage (12 volts), wherein the boosted voltage is used for erasing and writing of data. Throughout the present specification, the logic inversion of logic signals will be represented by adding a symbol# after the name of the signal.
In the conventional EEPROM 60' having a construction as such, the write control circuit 7 carries out the following processes when writing data.
(1) First, the write control circuit 7 activates the address latch 2 as well as the data latch 4 to cause a latching of the address data and the data supplied externally.
(2) Next, the control circuit 7 activates the high voltage generator 8 for erasing the memory cell selected by the address data held in the address latch 2. The interval of the erasing is controlled by the timer 6.
(3) Next, the control circuit 7 deactivates the high voltage generator 8 and waits for the high voltage in the chip to disappear. This interval is controlled by the timer 6.
(4) Further, the control circuit 7 activates the high voltage generator 8 once more to cause a writing of the data held in the data latch 4 into the memory cell selected by the address data held in the address latch 2. The interval for this writing process is controlled by the timer 6.
(5) Next, the control circuit 7 deactivates the high voltage generator 8 and waits for the high voltage in the chip to disappear. The interval for this process is controlled by the timer 6.
(6) Finally, the control circuit 7 activates the read circuit to carry out a comparing process for verifying the data read out from the selected memory cell with the data held in the data latch 4.
In the foregoing processes (1)-(6), there may be a case wherein a confirmation step is interposed between the step (3) and the step (4) for confirming that the memory cell is erased.
In the foregoing operation, it should be noted that the EEPROM 60' is disconnected from the system bus IBUS by the address latch 2 and the data latch 4 as well as by the write control circuit 7 until the writing is completed. In other words, the reading from the EEPROM 60' is impossible in such a system during the write interval for writing data into the EEPROM 60'.
When reading of data is attempted while writing is still being made in such a system, one obtains meaningless data such as "111111 . . . " In order to prevent this, there are EEPROMS 60' that issue a busy signal such as BUSY# during the write interval. In fact, the conventional system of FIG. 1 issues such a busy signal when writing data. Alternatively, there are other types of EEPROM that do not have an output terminal for the busy signal BUSY#. In this EEPROM, a logic inversion of the written data or a part of the same is outputted. In any of these conventional EEPROMs, the content of the data that is read out during the write interval is meaningless.
Conventionally, EEPROMs have primarily been used for data memories, while the device can also be used for a program memory. In fact, the use of EEPROMs as a program memory is increasing these days. In such a data processing system that uses an EEPROM for the memory in addition to the conventional ROM and RAM, a memory space shown in FIG. 5 may be constructed.
Referring to the memory space of FIG. 5, it will be noted that the EEPROM has a first address area A2-2 extending from 6000H to 6FFFH (the last H designates that the value preceding the same is a hexadecimal number) for data and a second memory area A2-1 extending from 7000H to 7FFFH for programs. More specifically, programs or subroutines that rewrite the content of the memory area A2-2 are stored in the memory area A2-1.
Next, the processing that occurs in a data processing system having such a memory space will be described with reference to FIG. 1 and a timing chart of FIGS. 2(A)-2(D). The processing of FIGS. 2(A)-2(D) includes the access of the EEPROM, wherein FIG. 2(A) shows the timing of the output enable signal OE#, FIG. 2(B) shows the timing of the write enable signal WE#, FIG. 2(C) shows the timing of the busy signal BUSY#, and FIG. 2(D) shows the timing of the data outputted on the data bus DBUS.
When the program counter 21 in the CPU 40 selects the program memory area A2-1 of the EEPROM 60', the instructions are read out consecutively from the EEPROM 60' and decoded by the instruction decoder 22. The instructions thus decoded are then executed by the execution unit 23.
When there is an instruction A for writing data D1 into the data memory area A2-2 of the EEPROM 60', the CPU 40 supplies the data D1 to the data bus DBUS and the address data to the address bus ABUS. Further, the CPU 40 activates the write enable signal WE#. In response to these, the EEPROM 60' starts the writing procedure according to the steps described before. During this interval for writing data (usually several milliseconds to several tens of milliseconds), the busy signal BUSY# is turned active as already noted. In the interval wherein the signal BUSY# is active, no normal reading operation from the EEPROM 60' is possible. When the reading of data is attempted during such an interval, the CPU 40 acquires meaningless data as instruction, and such erroneous data may cause a runaway of the system.
In order to eliminate the problem of malfunctioning of the system, conventional data processing systems have used one or more of the following remedies.
(1) Provide a plurality of EEPROMs in correspondence to the storage of programs and storage of data.
(2) Halt the CPU during the interval in which the busy signal BUSY# is active.
(3) Issue a hardware interrupt when the EEPROM has made a reading during the write interval.
The first option (1) to use plurality of EEPROMs obviously requires excessive cost and is disadvantageous from the view point of constructing the CPU 40 and the EEPROM 60' on a common monolithic chip. The second option (2), on the other hand, has an obvious disadvantage that the CPU 40 cannot carry out any processes while writing is being made into the EEPROM 60'. Thereby, the advantage of the system to disconnect the EEPROM 60' from the rest of the system by providing the write control circuit 7, disappears entirely. Further, the third option (3) for carrying out an interruption routine requires an exceptional process by software, while such a process, being a non-real time processing, causes a problem of software overhead.